The present invention generally relates to a television signal receiver, and more particularly, to a method for reducing noise interference in a phase lock loop (xe2x80x9cPLLxe2x80x9d) circuit in a tuner module of a television signal receiver while also permitting bi-directional communication between the tuner module and a controller unit.
A television system such as a high definition television (xe2x80x9cHDTVxe2x80x9d) system typically employs a front end comprising a tuner, a digital intermediate frequency (xe2x80x9cIFxe2x80x9d) circuit, and a digital demodulation integrated circuit (xe2x80x9cICxe2x80x9d). The system may be controlled from a microprocessor using an inter-integrated circuit (xe2x80x9cIICxe2x80x9dxe2x80x94typically pronounced xe2x80x9cI-squared Cxe2x80x9d) bus.
An IIC bus is a two line, bi-directional digital bus that permits two ICs to communicate on a bus path at a time. An IC serving in a xe2x80x9cmasterxe2x80x9d mode of operation, initiates a data transfer operation on the bus and generates clock signals that permit the data transfer. An IC serving in a xe2x80x9cslavexe2x80x9d mode of operation is the IC being operated on or communicated to by the master IC, whereby the slave IC is instructed to either send or receive data. Each IC has its own unique address and the master IC initiates and terminates the communications.
A serial clock line (xe2x80x9cSCLxe2x80x9d) propagates clock signals on the IIC bus from a master IC to a slave IC. Each master IC typically generates its own clock signals when transferring data on the bus. A second bi-directional line of the IIC bus is typically a serial data line (xe2x80x9cSDAxe2x80x9d) that transfers data using serial digital transactions. Typically, one or more bits are used as acknowledgment bits. According to an exemplary design, when both the SCL and SDA are held in a logic high state, no data can be transferred between two ICs on the IIC bus. A transition from a logic high state to a logic low state on the SDA, while the SCL is in a logic high state, indicates a start condition for the exchange of digital data over the IIC bus. Conversely, a transition from a logic low state to a logic high state on the SDA, while the SCL is in a logic high state, indicates a stop condition. The master IC typically generates one clock pulse for each bit of digital data transferred on the SDA, and a logic state on the SDA can only change when the clock signal on the SCL is in a logic low state.
Multiple ICs typically share an IIC bus. For example, a microprocessor in a controller of a television signal receiver communicates with numerous ICs within the receiver using an IIC bus. This communication, however, can create operational problems within the television receiver. In particular, coincidental bus traffic by the microprocessor, which functions as a master IC, has been found to cause phase noise interference in a tuner of the television receiver. More specifically, phase noise interference may be introduced to a PLL of the tuner that is serially coupled to the IIC bus. The PLL operates as a frequency variable tone generator, and the microprocessor controls the oscillator frequency of the PLL via the IIC bus. The PLL is susceptible to bus traffic when the microprocessor sends commands to other ICs on the bus, so that instead of producing a tone locked at a specific desired frequency, a range of other frequencies around the desired tone frequency are produced.
For example, in a PLL having a 4 MHz oscillator, any incidental noise signals generated by the microprocessor may be received by other pins of the PLL IC connected to the IIC bus. This noise is added to the resultant frequency. Accordingly, in a situation where a user selects a channel at 701 MHz and the television system requires a down-converted IF signal at 44 MHz, then the PLL must generate a tone locked at a frequency of 745 MHz. Normally, the 701 MHz television signal and the 745 MHz tone signal are mixed to produce an IF signal locked at 44 MHz. However, additional noise will generate other harmonic frequencies around the tone frequency, thereby causing the IF signal to instead fluctuate in a range around 44 MHz.
As a result, the bus noise is added to the incoming digital video and/or audio signal and causes a degradation in bit error rate (xe2x80x9cBERxe2x80x9d) performance of the television receiver. Ultimately, the bit errors can manifest themselves as additional or missing luminance and chrominance pixel components in the video the user is viewing, as well as cause xe2x80x9cclicks and popsxe2x80x9d in the audio output. Similarly, when processing an analog television signal, the IIC bus noise can cause distorted images and/or undesirable wow and/or flutter in the audio output.
Phase noise interference caused by the IIC bus traffic may be compensated somewhat by widening the bandwidth of the demodulation IC""s carrier tracking loop, to allow it to xe2x80x9ctrack outxe2x80x9d the corruption. However, such a method may allow additional low frequency noise to combine with the video and/or audio signal, thereby degrading the BER of the television receiver.
An apparatus and method for isolating the noise caused by the IIC bus traffic is described in an international application entitled xe2x80x9cMethod and Apparatus for Isolating IIC Bus Noise from a Tuner in a Television Receiverxe2x80x9d filed Dec. 22, 1999, having application No. PCT/US99/30775. The apparatus described therein provides an isolation buffer that allows the receiver to only pass data to the tuner""s phase-lock loop IC when a tune command is issued by a microprocessor. In one embodiment, the isolation buffer comprises a pair of OR gates having respective inputs coupled to the microprocessor and respective outputs coupled to the tuner module. Such an apparatus is suitable when the microprocessor is sending commands to the tuner module. However, there may be situations when is it desired to transmit data from the tuner module to the microprocessor. For example, the tuner module may be a part of a circuit board that includes a EEPROM that includes information required by the microprocessor during tuning events.
Accordingly, there is a need for an improved way to prevent the IIC bus noise from adversely influencing the PLL circuitry of the tuner. In fulfilling this need, however, it is desirable that the microprocessor be able to both transmit and receive signals to and from the tuner and its associated components. Such bi-directional communication capability can, for example, enable the microprocessor to control the operation of the television receiver in a more effective manner, and also allow for more effective placement of components since the components requiring noise isolation may be placed on the same circuit board with components that require bi-directional communications capability with the main processing unit. The present invention addresses these and other issues.
In accordance with the present invention, an apparatus for isolating a tuner module having a noise intolerant device from a source of noise is provided. The apparatus comprises a digital bus. A processor outputs clock signals and first data signals and receives second data signals over the digital bus. A bi-directional buffer is coupled between the digital bus and the module, which includes the noise intolerant device and devices that include data that must be transferred to the processor. The apparatus operates such that, in dependence upon a control signal, the bi-directional buffer in a first mode of operation isolates the module from other components on the digital bus, and in a second mode of operation passes the clock signals and the data signals from the digital bus to the module, and passes data signals from the module to the digital bus.